This invention relates to an interfacing circuit arrangement for converting non-TTL signals into signals which are compatible with TTL-type logic. More particularly, it involves a high speed CML/ECL to TTL converter which operates at high speed.
In the design of large scale integrated circuit chips, it would be advantageous to be able to freely intermix different types of logic, for example, emitter coupled logic (ECL), current mode logic (CML), and transistor-transistor logic (TTL). However, the various types of logic operate on different voltage or signal levels. The precise levels differ from manufacturer to manufacturer but generally the difference between the two ECL/CML levels is less than the difference between the two TTL levels. The design of integrated circuit chips does not lend itself to employing two different power supply levels, one for the CML/ECL logic and another for the TTL logic. Consequently, in a single power supply chip, the CML/ECL logic signals must be converted back to TTL signals when the two types of logic are interfaced. The CML/ECL signals generally reference close to the power supply voltage, Vcc. By way of example, if the supply voltage Vcc is 5.0 volts, the two CML/ECL voltage levels might be 5.0 volts and 4.2 volts. In contrast, the TTL signals reference close to ground potential. Consequently, the two TTL signal levels might be at Vcc or 5.0 volts and 0.0 volts or ground. Hence it can be seen that the 4.2 volts CML/ECL voltage low level must be converted to a ground potential low level for the TTL gate. Conventional techniques have sensed a single ended CML/ECL signal and translated the signal through an extra level shifting network to provide a zero volt TTL signal when it sensed a 4.2 volt CML/ECL signal. The shifting network unfortunately adds extra delay to the conversion process. Furthermore, this technique requires tight design and process tolerances to maintain the CML/ECL voltage levels within closely defined voltages. For example, if the power supply, Vcc, has a wide tolerance then the prior art converter cannot distinguish between the high and low CML/ECL voltage levels. Moreover, since this technique senses only a single ended voltage swing on the preceding CML/ECL gate, the converter is susceptible to noise in the data transmission which can hamper proper operation.
U.S. Pat. No. 3,766,406 Bryant et al discloses such a prior art converter circuit. In addition to the above mentioned drawbacks, it requires a relatively large CML/ECL voltage swing in order to insure accurate conversion. This large voltage swing adds additional delay to the circuit. It would be advantageous to provide a CML/ECL to TTL converter that is capable of operating on a smaller voltage swing, preferably 400 mv, thereby increasing the speed of the circuit.